Elevator controller and controlling method

ABSTRACT

An elevator control device has: a processing portion for controlling an operation of an elevator based on a clock signal; and a detection portion for comparing the number of edges of the clock signal counted within a preset period of time with the preset number of edges to detect a condition of the clock signal to issue an instruction related to the operation of the elevator to the processing portion in accordance with the detection results.

TECHNICAL FIELD

The present invention relates to an elevator control device and anelevator control method for controlling an operation of an elevator.

BACKGROUND ART

In a conventional counter of an elevator control device, as described inJP 53-89149 A for example, when a counted value of a clock signalreaches a preset value, a counting circuit outputs a coincidence signalrepresenting that both the values have coincided with each other to anoutput circuit. Then, the counting circuit outputs the coincidencesignal to the output circuit, thereby adjusting timing at which theelevator control device controls an operation of the elevator.

However, for example, when the clock signal been moved to an abnormalstate due to a stop or the like of the clock signal, the countingcircuit cannot determine the counted value of the clock signal bycalculation, and thus the elevator control device cannot properlycontrol the operation of the elevator.

The present invention has been made in order to solve the inconvenienceas described above, and it is, therefore, an object of the presentinvention to obtain an elevator control device and an elevator controlmethod which are capable of suitably controlling an operation of anelevator in accordance with an operational condition of a clock signal.

DISCLOSURE OF THE INVENTION

According to one aspect of the present invention, there is provided anelevator control device, comprising: a processing portion forcontrolling an operation of an elevator based on a clock signal; and adetection portion for detecting a condition of the clock signal countedwithin a preset period of time to issue an instruction related to theoperation of the elevator to the processing portion based on thecondition of the clock signal detected.

According to another aspect of the present invention, there is providedan elevator control device, comprising: a processing portion forcontrolling an operation of an elevator based on a clock signal; acounter portion for counting the number of edges of the clock signalwithin a present period of time; a setting portion for setting thenumber of edges of the clock signal as a reference to be used fordetecting a condition of the clock signal; and a detection portion forcomparing the number of edges counted by the counter portion with thenumber of edges set in the setting portion to detect the condition ofthe clock signal to issue an instruction related to the operation of theelevator to the processing portion in accordance with the condition ofthe clock signal detected.

According to a still further aspect of the present invention, there isprovided an elevator control method, comprising: a control step forcontrolling an operation of an elevator based on a clock signal; adetection step for detecting a condition of the clock signal countedwithin a preset period of time; and an instruction step for issuing aninstruction related to the operation of the elevator based on resultsdetected through the detection step.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an elevator control device accordingto an embodiment of the present invention; and

FIG. 2 is a flow chart showing an operation of the elevator controldevice shown in FIG. 1.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be describedbased on the drawings.

FIG. 1 is a block diagram showing an elevator control device 100according to an embodiment of the present invention. In this embodiment,a description will be given on the assumption that the elevator controldevice 100 is incorporated in an elevator control panel.

In FIG. 1, the elevator control device 100 has a microcomputer(processing portion) 1, a counter portion 2, a frequency divider 3, asetting portion 4, a detector (detection portion) 5, and watch dog timer(WDT) 6.

The microcomputer 1 controls a control apparatus group 7 and a safetydevice/apparatus group 8 synchronously with a clock signal d1 so as tomaintain the elevator in a safe state. In this embodiment, a process inwhich the microcomputer 1 carries out the control is referred to as acontrol step.

The control apparatus group 7 includes, for example, a motor (drivingportion) 7 a for a traction machine. In addition, the safetydevice/apparatus group 8 includes, for example, a brake device 8 a and agovernor 8 b.

The clock signal d1 is a signal which is alternately repeated in a highlevel and a low level at regular intervals, and is generated by agenerator (not shown). In addition, the clock signal d1 has a risingedge and a trailing edge of a voltage. In this embodiment, themicrocomputer 1, for example, operates synchronously with the risingedge of the voltage of the clock signal d1. In other words, the clocksignal d1 is used as a driving clock of the microcomputer 1.

For example, the microcomputer 1 counts the number of pulses obtained inan encoder of the motor 7 a or counts the number of pulses obtained inan encoder of the governor 8 b, within a predetermined period of theclock signal d1, to control a speed arithmetic operation or an operationof a car.

The counter portion 2 counts the number of rising edges of the clocksignal d1. In this embodiment, the counter portion 2 counts the numberof rising edges of the clock signal d1 every predetermined period inaccordance with a trigger signal d2, a frequency of which is convertedinto a predetermined frequency by the frequency divider 3. Note that thetrigger signal d2 is generated by a generator (not shown).

More specifically, the counter portion 2 counts the number of risingedges of the clock signal d1 using the rising edge of the trigger signald2, which is alternately repeated in a high level and a low level atregular intervals, as a trigger. That is, the counter portion 2 countsthe number of rising edges of the clock signal d1 with setting a periodof time from an arbitrary rising edge of the trigger signal d2 to a nextrising edge of the trigger signal d2 as one period.

The frequency divider 3 converts the frequency of the trigger signal d2into the predetermined frequency, thereby making the number of edges ofthe clock signal d1 easy to count.

The setting portion 4, for example, is a register or the like. Thenumber of edges d3 of the clock signal d1 in a normal state is set inthe setting portion 4 in advance by the microcomputer 1. The number ofedges d3 of the clock signal d1 is a reference value used for detectinga condition of the clock signal d1, i.e., normality or abnormality ofthe clock signal d1. The number of edges d3 of the clock signal d1 canbe changed to an arbitrary value by the microcomputer 1. In thisembodiment, “the number of edges of the clock signal d1 in the normalstate” between two rising edges of the trigger signal d2 is set as thenumber of edges d3 in advance.

Note that the number of edges d3 is registered in the setting portion 4by the microcomputer 1 when an operator specifies the number of edges d3to be set in the setting portion 4 by manipulating the microcomputer 1,for example. In this embodiment, a process for setting the number ofedges d3 in the setting portion 4 is referred to as a setting step.

The detector 5 transmits a signal to the microcomputer 1 in accordancewith the condition of the clock signal d1, i.e., the normality orabnormality of the clock signal d1. The detector 5 includes a comparisonportion 5 a and an instruction portion 5 b. Functions of the comparisonportion 5 a and the instruction portion 5 b are as follows.

The comparison portion 5 a compares the number of edges counted by thecounter portion 2 with the number of edges set in the setting portion 4to detect the condition of the clock signal d1. The instruction portion5 b transmits a signal related to the abnormality or normality to themicrocomputer 1 in accordance with the detection results obtained by thecomparison portion 5 a.

The WDT 6 monitors the microcomputer 1. More specifically, when thepulse from the microcomputer 1 has not been inputted for a preset periodof time, i.e., when the microcomputer 1 is unable to operate, the WDT 6outputs a reset signal to the microcomputer 1.

FIG. 2 is a flow chart showing a method of controlling the elevatorcontrol device 100.

The counter portion 2 counts the number of rising edges of the clocksignal d1, with which the microcomputer 1 operates in synchronization (acount step 101).

The count portion 2 continues to count the number of rising edges of theclock signal d1 unless the counter portion 2 receives an input of therising edge of the trigger signal d2, the frequency of which isconverted into the predetermined frequency by the frequency divider 3.That is, the counter portion 2 counts the number of rising edges of theclock signal d1 every interval of the rising edges of the trigger signald2.

Then, when receiving an input of the rising edge of the trigger signald2 (an input step 102), the counter portion 2 latches a counted valueindicating the number of edges counted by the counter portion 2 andtransfers the counted value thus latched to the detector 5 (a transferstep 103). Then, the counter portion 2 resets the counted value (a resetstep 104).

Next, the comparison portion 5 a compares the counted value transferredthereto from the detector 5 with the value indicated by the number ofedges d3 which is set in the setting portion 4 in advance (a comparisonstep 105) to judge whether or not an error between the counted value andthe value indicated by the number of edges d3 falls within a presetallowable range (e.g., within ±2%) (a judgment step 106). That is, thecomparison portion 5 a detects the condition of the clock signal d1,i.e., abnormality or normality of the clock signal d1 through thecomparison step 105 and the judgment step 106. Note that the comparisonstep 105 and the judgment step 106 are collectively referred to as adetection step.

Then, when it is judged in the comparison portion 5 a that the errorbetween both the values falls within the allowable range, theinstruction portion 5 a transmits a signal representing normality of theclock signal d1 to the microcomputer 1. On the other hand, when it isjudged in the comparison portion 5 a that the error between both thevalues is out of the allowable range, the instruction portion 5 atransmits a signal representing abnormality of the clock signal d1 tothe microcomputer 1 (an output step 107). Note that the comparisonportion 5 a may clear the counted value in the counter portion 2 when itis judged in the comparison portion 5 a that the error between both thevalues falls within the allowable range.

Next, the microcomputer 1 outputs a predetermined instruction signal toat least one of the control apparatus group 7 and the safetydevice/apparatus group 8 in accordance with the signal issued by theinstruction portion 5 b (an instruction step 108).

For example, the microcomputer 1 outputs an instruction signal to stopthe motor 7 a in accordance with the signal issued by the instructionportion 5 b. In addition, the microcomputer 1 outputs an instructionsignal to the brake device 8 a to cause the brake device 8 a to carryout the braking operation. Thus, the microcomputer 1 outputs theinstruction signal to any one of the control apparatus group 7 and thesafety device/apparatus group 8, thereby stopping the car.

As described above, in the elevator control device 100 of thisembodiment, the microcomputer 1 has the control step for controlling theoperation of the elevator based on the clock signal d1. The counterportion 2 has the count step for counting the number of edges of theclock signal d1 within the predetermined period of time based on thetrigger signal d2. In addition, the detector 5 has the detection stepfor detecting the condition of the clock signal d1 by comparing thenumber of edges counted by the counter portion 2 with the number ofedges d3 set in the setting portion 4, and the instruction step forissuing the instruction related to the operation of the elevator to themicrocomputer 1 in accordance with the detection results.

For this reason, when the abnormality of the clock signal d1 is detectedby the detector 5, the microcomputer 1 can carry out the control so asto suitably drive the control apparatus group 7 and the safetydevice/apparatus group 8. Accordingly, the microcomputer 1 can suitablycontrol the operation of the elevator in accordance with the operationalcondition of the clock signal d1.

Further, the detector 5 detects the operational condition of the clocksignal d1 based on the number of edges of the clock signal d1.Therefore, unlike the case of the WDT 6, even when the period of theclock signal d1 is shortened (in case of shortening of the period), thedetector 5 can detect this situation as the abnormality of the clocksignal d1. In addition, for example, when the period of the clock signald1 is lengthened and when the clock signal d1 is stopped, the detector 5can detects those situations as the abnormalities of the clock signald1. For this reason, the microcomputer 1 can carry out the control so asto suitably drive the control apparatus group 7 and the safetydevice/apparatus group 8 in accordance with various abnormalities of theclock signal d1.

For example, even when the period of the clock signal d1 changes from 10ms to 5 ms, a situation can be prevented where the microcomputer 1misinterprets a decrease in number of pulses obtained in the encoder ofthe motor 7 a as that the speed of the car is reduced to half of thenormal speed and causes the car traveling at an over-speed to collidewith a buffer.

In addition, the detector 5 compares the number of edges of the clocksignal d1 counted within the preset period of time with the presetnumber d3 of edges to detect the condition of the clock signal d1, andissues the instruction related to the operation of the elevator to themicrocomputer 1 in accordance with the detection results. Thus, themicrocomputer can suitably control the operation of the elevator inaccordance with the operational state of the clock signal d1.

In addition, when detecting the abnormality based on the detection ofthe condition of the clock signal d1, the detector 5 issues theinstruction to the microcomputer 1 to stop the motor 7 a. Thus, when theclock signal d1 enters the abnormal state, the motor 7 a is stopped tostop the car so that the car enters the safe state.

Also, when detecting the abnormality based on the detection of thecondition of the clock signal d1, the detector 5 issues the instructionto the microcomputer 1 to cause the brake device 8 a to carry outcontrol operation. Thus, when the clock signal d1 enters the abnormalstate, the car is stopped by the braking operation of the brake device 8a so that the car becomes the safe state.

Moreover, since the number of edges d3 set in the setting portion 4 canbe changed to an arbitrary value, the detector 5 can detect theoperational condition of the clock signal d1 in accordance with theclock signal having various frequencies.

Note that in the above-mentioned embodiment, when detecting the stop ofthe clock signal d1 as the abnormality of the clock signal d1, thedetector 5 may issue an instruction to the microcomputer 1 to stop theoperation of the elevator. In this case, when the clock signal d1 stops,the car is stopped so that the elevator is moved to the safe state.However, when the microcomputer 1 is inoperable due to the stop of theclock signal d1, the WDT 6 may output an interrupt signal to themicrocomputer 1 to reset the microcomputer 1.

In addition, the case has been described where the counter portion 2counts the number of rising edges of the clock signal d1. However, forexample, the counter portion 2 may count the number of the trailingedges of the clock signal d1.

Also, the case has been described where the frequency divider 3 changesthe frequency of the trigger signal d2. However, for example, thefrequency divider 3 may change the frequency of the trigger signal d2.

1. An elevator control device, comprising: a processing portion for controlling an operation of an elevator based on a clock signal; and a detection portion for detecting a condition of the clock signal counted within a preset period of time to issue an instruction related to the operation of the elevator to the processing portion based on the condition of the clock signal detected.
 2. The elevator control device according to claim 1, wherein the detection portion issues an instruction to the processing portion to stop the operation of the elevator when detecting an abnormality based on detection of the condition of the clock signal.
 3. The elevator control device according to claim 1, wherein the detection portion issues an instruction to the processing portion to stop the driving portion of the elevator when detecting an abnormality based on detection of the condition of the clock signal.
 4. The elevator control device according to claim 1, wherein the detection portion issues an instruction to the processing portion to cause the brake device to carry out control operation of the elevator when detecting an abnormality based on detection of the condition of the clock signal.
 5. The elevator control device according to claim 1, wherein the detection portion compares the number of edges of the clock signal with the preset number of edges when detecting the condition of the clock signal counted within the preset period of time.
 6. The elevator control device according to claim 5, wherein the preset number of edges can be changed to an arbitrary value.
 7. An elevator control device, comprising: a processing portion for controlling an operation of an elevator based on a clock signal; a counter portion for counting the number of edges of the clock signal within a present period of time; a setting portion for setting the number of edges of the clock signal as a reference to be used for detecting a condition of the clock signal; and a detection portion for comparing the number of edges counted by the counter portion with the number of edges set in the setting portion to detect the condition of the clock signal to issue an instruction related to the operation of the elevator to the processing portion in accordance with the condition of the clock signal detected.
 8. An elevator control method, comprising: a control step for controlling an operation of an elevator based on a clock signal; a detection step for detecting a condition of the clock signal counted within a preset period of time; and an instruction step for issuing an instruction related to the operation of the elevator based on results detected through the detection step.
 9. The elevator control method according to claim 8, wherein when it is detected through the detection step that the condition of the clock signal is abnormal, an instruction to stop the operation of the elevator is issued through the instruction step.
 10. The elevator control method according to claim 8, wherein when it is detected through the detection step that the condition of the clock signal is abnormal, an instruction to stop the driving portion of the elevator is issued through the instruction step.
 11. The elevator control method according to claim 8, wherein when it is detected through the detection step that the condition of the clock signal is abnormal, an instruction to cause the brake portion to carry out control operation of the elevator is issued through the instruction step.
 12. The elevator control method according to claim 8, wherein the number of edges of the clock signal counted within the preset period of time is compared with the preset number of edges through the detection step.
 13. The elevator control method according to claim 12, further comprising a setting step for setting the preset number of edges to an arbitrary value. 